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The following lab sheets are available:

for older lab sheets see here

• An Introduction to Unix for CAD Users
  • NoMachine Version
  • X2go Version

• Guides
  • Naming Conventions for CAD
  • Hierarchy Rules for Layout
  • Drawing Circuit Schematics
  • Drawing Stick Diagrams
  • Race Hazards, Clock Skew, Cross Simulation & Intra-Assignment Delays
  • Cell Characterization using HSpice -- early draft
  • Mark Zwolinski's notes on ASM charts
• Magic
  • Introduction to Magic v8
    — Inverter Design Animation
    • old version of introduction for Magic v7.1
  • Checking Magic Cells
  • Hierarchy
  • Simulation with SystemVerilog
    • old version using NC-Verilog for SystemVerilog
    • old version using NC-Verilog for Verilog
  • Simulation with HSpice
    • old versions including the use of CosmosScope or AvanWaves graphics.
  • Printing using Flea
  • Design Rule Checking using Cadence Assura
    • AMS C35B4 Version
  • Design Rule Checking using Mentor Calibre
    • AMS C35B4 Version
  • Synthesis
• SystemVerilog
  • SystemVerilog Simulation
    • old version using NC-Verilog
  • Hardware Modelling with SystemVerilog
    • alternative version using packages
    • old version using NC-Verilog
• Verilog
  • Verilog Simulation
    • old version including the use of Verilog-XL graphics
  • Hardware Modelling with Verilog HDL
    • old version including the use of Verilog-XL graphics
• Spice
  • Spice Simulations
• Cadence
  • SystemVerilog Synthesis for Custom Target Library (using Genus)
    • old version using RTL Compiler
  • Cadence Place & Route using AMS 0.35µm Libraries -- early draft
  • Xilinx FPGA Design using Cadence Schematic Capture
  • Xilinx FPGA Design Synthesis from Verilog HDL
• L-Edit
  • L-Edit Place & Route
  • L-Edit <-> Magic Conversion
  • L-Edit User Guide

• AMS 0.35µm Design Flow
  • Preparing a pad ring for Synthesis -- not yet available
  • SystemVerilog Synthesis for AMS 0.35µm Libraries (using RTL Compiler) -- not yet available
  • Cadence Place & Route using AMS 0.35µm Libraries -- early draft

• System On Chip Design
  • ARM ASIC Version
    • (simplified)
  • ARM FPGA Version
    • (simplified)
  • ARM Altera FPGA Version
    • (simplified)

  • RISC-V ASIC Version
    • (simplified)
  • RISC-V FPGA Version
    • (simplified)
  • RISC-V Altera FPGA Version
    • (simplified)

• Design Rule Documents
• SystemVerilog Reference
• SystemVerilog Hypertext BNF
• Bucknell Verilog Manual
• VeriWell Help (for Motif version: mveriwell)

• (from the Universty of Edinburgh)
• (from ISS/iSolutions)
• (from ISS/iSolutions)
• (training manaual)