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VLSI Design Project

Lecture Notes

• Pad Ring and Floor Planning

• Full Chip Synthesis

Lab Resources

• Basel Halak's notes on RTL Synthesis using Design Compiler
  • Required source files:
    • qmults.v
    • .synopsys_dc.setup

• Full Chip Synthesis Demo
  • IO definition file used in this demo:
    • padring.txt
      - from which we can generate:
      • cpu.io
      • cpu.sv
  • Design files used in this demo:
    • src/ sub-directory contains SystemVerilog model files
      - note that this includes the cpu.sv file generated by process_pad_ring
    • files used to simulate this design:
      • system/ sub-directory contains SystemVerilog testbench files
      • simulate script runs the simulation
  • Required script files:
    • dc_script.tcl
    • demo_prepare_edi
    • edi_script.tcl
  Running the command init_ams_demo will copy the relevant files into ~/design/ams/ams_demo