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Full Custom Design Exercise

Syllabus and Overview

Overview for Part III Students making Option Choices

The following documents are available:

• 2013-2014

  Teams and Declaration of Specialisms

  • Blank Declaration of Specialisms Form

  Full custom design exercise 2014

  • Microprocessor Specification 2014

  • Programs

  • Simulation Environment

  Lecture Notes

  • Introduction
  • Basic Processor Design
    • older longer version
    • Instruction Set Terminology
  • Datapath Design
  • Advanced Bitslice Design
  • ASM Design for Processor Examples
  • Pad Ring and Floor Planning

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  Research Phase

  • Microprocessor Research

    • Deliverable: Individual Report
      • Referencing Your Work - study skills document published by the University

    • Submission Details:

      • Two PDF files submitted via:
        1. Full Report (including title page/table of contents/list of references/bibliography/appendices):
        2. Main Body of Report (not including title page/table of contents/list of references/bibliography/appendices):

      • Paper Copy of Full Report submitted via: Zepler Reception Drop Box

      • Single PDF file submitted via:
        1. Main Body of Report (not including title page/table of contents/list of references/bibliography/appendices):

    • Completion: 4.00 p.m., Wednesday 19^th February 2014

  • Simulations

  • Related Lecture Material

  • Example Outline Designs

    • RISC #1
      • Fixed 16 bit (= 1 word) Instruction Length
      • Register-Register Architecture
      • Pure 3 Address Architecture
      • 3 General Purpose Registers (+ R0 dummy register)
      • Single Status Flag: Carry
      • Short Immediates in the range -64 to +63
      • Long Immediates (10 bits) used for Set High and Branch instructions

    • RISC #2
      • Fixed 16 bit (= 1 word) Instruction Length
      • Register-Register Architecture
      • 2/3 Address Architecture
      • 7 General Purpose Registers (+ R0 dummy register)
      • All Immediates 8 bits long

    • CISC
      • Variable Length Instructions (1 or 2 words)
      • Register-Memory Single Address Architecture
      • 3 Special Purpose Registers: A, X, SP
      • 7 Addressing Modes: Immediate, Direct, Indexed with X, Indexed with SP, Stack(Pop/Push) + Inherent + PC Relative.

    • Hybrid RISC
      • RISC style processor but with variable length instructions
      • Variable Length Instructions (1 or 2 words)
      • Pure 3 Address Architecture
      • 6 General Purpose Registers (+ PC + R0)
      • Single Status Flag: Carry
      • All Immediates 16 bits long
      • No special control tranfer instructions

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  Design Phase

  • Initial Design

    • Deliverables: Instruction Set Summary and Datapath Diagram
      • Stapled together with a cover sheet - ring binding not required.
      • To school office.
    • Completion: 4.00 p.m., Wednesday 26^th February 2014

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  Implementation Phase

  • SystemVerilog Behavioural Model

    • Deliverables: Behavioral Files and Program Files

      • Multiply Program
      • Interrupt Program (optional)
      • Hand-in Script

    • Completion: 4.00 p.m., 5^th March 2014 10.00 a.m., 6^th March 2014

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  • Cross Simulation

    • Deliverables: Magic Files, SystemVerilog Files and Program Files

      • Multiply Program
      • Interrupt Program (optional)
      • Hand-in Script

    • Completion: 4.00 p.m., 12^th March 2014

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  • Pad Ring and Final Routing
    • Empty pad ring (minimum size): pad_ring.mag

    • Alternatively create your own pad ring:

          create_pad_ring <x_core_size> <y_core_size>
      

      if your design doesn't support interrupts the correct command is:

          create_pad_ring -nointerrupt <x_core_size> <y_core_size>
      

    • Header file for full structural simulation: cpu.sv

    • Magic netlist for final routing: cpu.net -- Read this file before using it.

    • Dummy cpu_core for routing tests: cpu_core.mag

  • Postprocessing a Magic Design
    • Example pad ring showing n-well/n-ohmic guard ring: pad_ring_example.mag

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  • Electronic Hand-in Procedure for Final Design

    • Deliverables: Magic Files, SystemVerilog Files and Program Files

      • Multiply Program
      • Factorial Program
      • Random Program
      • Interrupt Program (optional)
      • Hand-in Script

    • Completion: 4.00 p.m., 2^nd May 2014

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  Documentation

  • Programmer's Guide
    • Programs
    • Report with and without Appendices:
    • Completion: 4.00 p.m., 2^nd May 2014

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  • Final Report
    • Report writing guidance from exercise introduction
      • Division of labour Form
    • Report with and without Appendices:
    • Report without Appendices:
    • Completion: 4.00 p.m., 13^th May 2014

• Links