This course aims to provide an understanding of basic VLSI layout and
circuit design principles. In particular, to look at how CAD tools are
utilized in designing digital integrated circuits.
For more details see the course
.
In addition to the syllabus, a course overview is provided for part III students making Options Choices.
Lecture Notes for 2025-2026:
- SystemVerilog Hardware Description Language
- ...unedited
- State Machine Design using SystemVerilog
- ...unedited
- Gate Matrix Design
- ...unedited
- Bitslice Design
- Pad Ring and Floor Planning
Assignments for 2025-2026:
- Mini Design Exercise 1 : Gate Design
-
-
Deadline 16:00 Wednesday 12th November
- Design Exercise 3
- Files Submission
- Deadline 16:00 Monday 1st December
Early submission of files will result in enhanced feedback.
-
- Characterisation and Cell Library Databook Documentation
- by Kostas Pagiamtzis
- Example Standard Cell Databook
- yours won't look like this one but it it is useful to see what a real cell library databook looks like.
- Design Exercise Report
- Documentation: Cell Library Databook + Design Exercise Report
- Design Exercise 4
-
-- how and why to use "#20" delays in your SystemVerilog controller
- For full chip routing: multiplier.net,
multiplier.sv
-- Not yet published
- Preparation for Handin
- Files Submission
- Deadline 16:00 Friday 9th January
Early submission of files will result in enhanced feedback.
-
- Supporting Figures
Laboratory Course:
Associated Lecture Course:
This course is closely associated with the
course which is either taken prior to or concurrently with this course.
| Master copy |
Copyright (c) Iain McNally 2023 |