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VLSI Design Project

When you'll study it
Semester 2
CATS points
15
ECTS points
7.5
Level
Level 7
Module lead
Iain McNally
Academic year
2026-27

Module overview

Design hierarchical modules using a layout editor. Demonstrate project management and time management skills including working to deadlines and planning your work beyond the next deadline. Communicate your work accurately and concisely through written reports.