Module overview
This modules provides an understanding of the design and layout of digital VLSI circuits and systems through laboratories and design exercises making use of appropriate CAD tools.
Aims and Objectives
Learning Outcomes
Knowledge and Understanding
Having successfully completed this module, you will be able to demonstrate knowledge and understanding of:
- The use of CAD tools in the design process
- The design of small digital systems using predfined cells
- The design of digital CMOS integrated circuit cells
Subject Specific Practical Skills
Having successfully completed this module you will be able to:
- Assemble CMOS cells to implement digital systems using a layout editor
- Verify the functionality and performance of CMOS designs using simulation tools
- Design digital systems using hardware description language
- Design digital CMOS cells using a layout editor
- Design test benches to verify digital systems using hardware description language
Subject Specific Intellectual and Research Skills
Having successfully completed this module you will be able to:
- Understand the principles of digital CMOS integrated circuit design
- Derive compact and efficient circuit structures to implement digital functions
Transferable and Generic Skills
Having successfully completed this module you will be able to:
- Perform basic tasks on a Unix workstation
- Collaborate with others to agree a common specification and share out work
- Communicate your work accurately and concisely through written reports
- Organise your work in a logical manner in a Unix filesystem
Syllabus
Layout for VLSI
- Cell layout
- Standard cell layout
- Full and semi-custom design
- Floorplanning
- Bit slice design
Digital design using SystemVerilog
- Introduction to SystemVerilog
- Design for Synthesis
CAD Tools & Techniques
- Magic VLSI layout editor
- HSpice analogue circuit simulator
- SystemVerilog Hardware Description Language and digital simulator
- Cadence IC design toolset
Learning and Teaching
Teaching and learning methods
.
| Type | Hours |
|---|---|
| Supervised time in studio/workshop | 36 |
| Follow-up work | 12 |
| Preparation for scheduled sessions | 12 |
| Lecture | 24 |
| Completion of assessment task | 56 |
| Wider reading or practice | 10 |
| Total study time | 150 |
Resources & Reading list
Textbooks
Weste N, Harris D (2011). Integrated Circuit Design: A Circuits and Systems Perspective. Pearson.
Assessment
Assessment strategy
The assessment is 100% coursework, consisting of four design assignments and an ongoing assessment of your laboratory work. Please note how the final mark is calculated. Assignment 1 - Design and optimisation of a CMOS gate using Magic (mini design exercise - no formal write-up) = max. 10 marks Assignment 2 - Design of a digital system using SystemVerilog HDL (mini design exercise - no formal write-up) = max. 10 marks Assignment 3 - Design of a standard cell library using Magic (team exercise - formal report) = max. 40 marks Assignment 4 - Bitslice Design using Magic and SystemVerilog HDL (individual exercise - basic documentation/just design diagrams) = max. 40 marks General laboratory performance (attendance/progress/up-to-date log book) = max. 25 marks FINAL MARK = (total marks for the four design assignments) x ( [75 + mark for general laboratory performance] / 100)Summative
This is how we’ll formally assess what you have learned in this module.
| Method | Percentage contribution |
|---|---|
| Coursework & Labs | 100% |
Referral
This is how we’ll assess you if you don’t meet the criteria to pass this module.
| Method | Percentage contribution |
|---|---|
| Coursework assignment(s) | 100% |
Repeat Information
Repeat type: Internal